Germanium-on-insulator (GOI) substrates may play an important role in future complementary metal oxide semiconductor (CMOS) scaling. In the semiconductor community, germanium (Ge) is widely recognized as having higher carrier mobility than silicon (Si) for both electrons and holes, as well as lower contact resistance and lower dopant activation temperatures that facilitate the formation of shallow junctions. The development of high-k dielectrics with a dielectric constant greater than silicon oxide (SiO2) for use as a gate insulator in metal oxide semiconductor field effect transistors (MOSFETs) is expected to provide a solution to the general poor quality of germanium oxide, which has historically represented a significant obstacle to the utilization of germanium in device fabrication.
MOSFETs may be manufactured using either bulk or silicon-on-insulator (SOI) substrates. The use of SOI substrates reduces parasitic junction capacitances and allows for greater channel currents that, in turn, allow for faster speeds than comparable devices fabricated in bulk silicon wafers. MOSFETs formed on SOI substrates have several additional advantages over comparable devices formed on conventional bulk substrates such as the elimination of latch-up, improved radiation hardness, and simplified device isolation and fabrication. The improved MOSFET device performance obtained with SOI substrates may also be expected with GOI substrates.
The large lattice constant mismatch between silicon and germanium precludes direct growth of epitaxial germanium on single crystal silicon without nucleation of a high density of defects such as threading dislocations. One traditional solution to this limitation is growth of compositionally graded layers where a large lattice constant mismatch is spread across several low-mismatch interfaces, thereby minimizing nucleation of threading dislocations. Compositional grading of relaxed Si1-xGex layers of increasing germanium fraction may be used to create an arbitrary lattice constant ranging from that of silicon to germanium on a bulk silicon substrate. Typically, a thick Si1-xGex buffer layer is grown on a silicon wafer and a thin strain-relaxed layer of Si1-xGex is grown on the buffer layer. By adjusting the deposition parameters for the Si1-xGex layers, the threading dislocations do not propagate vertically but instead propagate in the plane of the layers and subsequently end at the peripheral edges of the layers. A thin monocrystalline germanium active layer may be grown epitaxially on the relaxed layer of a similar lattice constant.
The first wafer with the monocrystalline germanium active layer is then bonded to a second bulk silicon wafer that is covered by an insulator layer, typically oxide. To that end, the monocrystalline germanium active layer is contacted with the insulator layer on the second wafer. The first wafer, the buffer layer, and the relaxed layer are then removed by grinding and/or etching, which leaves the monocrystalline germanium active layer on the buried insulator layer and thereby defines the GOI substrate.
There are several drawbacks associated with this conventional approach for forming GOI substrates. First, a significantly thick buffer layer is required, usually greater than one micrometer, to confine the threading dislocations and prevent their propagation into the monocrystalline germanium active layer. Growing a buffer layer of sufficient thickness to accomplish this objective requires an extensively long process duration and, therefore, the process throughput is limited. Second, a significant density of threading dislocations may nevertheless propagate from the buffer layer into the relaxed layer during epitaxial growth and/or during the subsequent thermal process. These threading dislocations may continue to propagate into the germanium layer, which results in a defective active layer for device formation. Third, the germanium concentration in the buffer layer has to be gradually increased during the epitaxial growth. Such precise control over the germanium concentration during buffer layer growth is technologically challenging. Finally, removing the relaxed layer selective to the monocrystalline germanium active layer is also challenging. Poor selectivity may cause undesired etching of the monocrystalline germanium active layer during removal of the relaxed layer, which may result in thickness variations.
What is needed, therefore, is a method for forming a semiconductor structure for use as a GOI substrate that overcomes the disadvantages of conventional methods of manufacturing such semiconductor structures, such as using compositionally graded layers to accommodate lattice mismatch.